Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with buried gates.
A process for fabricating a semiconductor device such as a memory device includes a device isolation process, which includes a Shallow Trench Isolation (STI) process.
According to the STI process, trenches are formed by using a hard mask layer as an etch barrier and etching a substrate. The formed trenches are filled with an insulation layer.
Under the hard mask layer, a pad oxide layer may be formed. The pad oxide layer is selectively removed after the device isolation process is completed.
FIGS. 1A to 1C illustrate a conventional method for fabricating a semiconductor device.
Referring to FIG. 1A, a pad oxide layer and a hard mask layer are sequentially stacked over a substrate 11 which includes a first region 101 and a second region 102.
The hard mask layer and the pad oxide layer are etched using a device isolation mask (not shown). Hereafter, the etched hard mask layer and the etched pad oxide layer are referred to as a first hard mask pattern 13 and a pad oxide layer pattern 12. Subsequently, trenches 14 are formed by etching the substrate 11 up to a certain depth by using the first hard mask pattern 13 as an etch barrier. The trenches 14 may be formed both in the first region 101 and the second region 102, and the trenches 14 formed in the second region 102 may have wider width than those formed in the first region 101. The first region 101 includes a cell region, while the second region 102 includes a peripheral circuit region.
An insulation layer is formed over the substrate 11 to gap-fill the trenches 14 and a planarization process is performed. As a result, a device isolation layer 15 gap-filling the trenches 14 is formed.
Referring to FIG. 1B, an open process of opening the first region 101 is performed on the resulting structure shown in FIG. 1. A capping layer is formed over the substrate 11, and a cell region open mask 17 is formed using a photoresist pattern. Subsequently, the capping layer of the first region 101 is etched so that the capping layer remains in the second region 102. Hereafter, the capping layer remaining in the second region 102 is referred to as a capping layer pattern 16.
Referring to FIG. 1C, the cell region open mask 17 is removed, and then the first hard mask pattern 13 of the first region 101 is selectively removed using the capping layer pattern 16 as a protective layer.
Subsequently, the pad oxide layer pattern 12 of the first region 101 is removed. Processes of forming landing plugs and buried gates (BG) in the first region 101 are performed. As described above, in the process for fabricating a semiconductor device including buried gates and landing plugs, the second region 102 is protected using the capping layer pattern 16 when the pad oxide layer pattern 12 is removed.
According to the above-discussed conventional technology, when the pad oxide layer pattern 12 is removed, a large difference in step height may be caused between the first region 101 and the second region 102. The difference in the step heights of the first and second region 101 and 102 is caused by the capping layer pattern 16 capping the second region 102. When the pad oxide layer pattern 12 is removed, a portion of the device isolation layer 15 may be removed as well. Since the device isolation layer 15 of the second region 102 is protected by the capping layer pattern 16, the large difference in the step height is caused, referring to a reference numeral ‘103’.
The step height difference 103 brings about failure in a subsequent process. For example, during a separation process using Chemical Mechanical Polishing (CMP), it is difficult to maintain the height of a separated layer at a uniform level. On the contrary, when the separation process is performed excessively to maintain the height of the separated layer at a uniform level, the height of the device isolation layer 15 remaining in the second region 102 may not be maintained uniformly. Furthermore, the step height difference 103 can deteriorate the stability of a subsequent process.